NXP Semiconductors /LPC15xx /SYSCON /SYSAHBCLKCTRL0

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Interpret as SYSAHBCLKCTRL0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RESERVED)SYS 0 (DISABLE)ROM 0 (RESERVED)RESERVED 0 (DISABLE)SRAM1 0 (DISABLE)SRAM2 0 (RESERVED)RESERVED 0 (DISABLE)FLASH 0 (DISABLE)FMC 0 (DISABLE)EEPROM 0 (RESERVED)RESERVED 0 (DISABLE)PMUX 0 (DISABLE)SWM 0 (DISABLE)IOCON 0 (DISABLE)GPIO0 0 (DISABLE)GPIO1 0 (DISABLE)GPIO2 0 (RESERVED)RESERVED 0 (DISABLE)PINT 0 (DISABLE)GINT 0 (DISABLE)DMA 0 (DISABLE)CRC 0 (DISABLE)WWDT 0 (DISABLE)RTC 0 (RESERVED)RESERVED 0 (DISABLE)ADC0 0 (DISABLE)ADC1 0 (DISABLE)DAC 0 (DISABLE)CMP 0 (RESERVED)RESERVED

DAC=DISABLE, ADC0=DISABLE, RTC=DISABLE, GPIO1=DISABLE, CRC=DISABLE, PMUX=DISABLE, FLASH=DISABLE, SRAM1=DISABLE, ADC1=DISABLE, GPIO0=DISABLE, SWM=DISABLE, IOCON=DISABLE, SRAM2=DISABLE, ROM=DISABLE, EEPROM=DISABLE, SYS=RESERVED, GINT=DISABLE, FMC=DISABLE, CMP=DISABLE, WWDT=DISABLE, DMA=DISABLE, PINT=DISABLE, GPIO2=DISABLE

Description

System clock control 0

Fields

SYS

Enables the clock for the AHB, the APB bridges, the Cortex-M3 core clocks, SYSCON, reset control, SRAM0, and the PMU. This bit is read-only and always reads as 1.

0 (RESERVED): Reserved

1 (ENABLE): Enable

ROM

Enables clock for ROM.

0 (DISABLE): Disable

1 (ENABLE): Enable

RESERVED

Reserved

SRAM1

Enables clock for SRAM1.

0 (DISABLE): Disable

1 (ENABLE): Enable

SRAM2

Enables clock for SRAM2.

0 (DISABLE): Disable

1 (ENABLE): Enable

RESERVED

Reserved

FLASH

Enables clock for flash memory.

0 (DISABLE): Disable

1 (ENABLE): Enable

FMC

Enables clock for flash controller.

0 (DISABLE): Disable

1 (ENABLE): Enable

EEPROM

Enables clock for EEPROM.

0 (DISABLE): Disable

1 (ENABLE): Enable

RESERVED

Reserved

PMUX

Enables clock for pin mux.

0 (DISABLE): Disable

1 (ENABLE): Enable

SWM

Enables clock for switch matrix.

0 (DISABLE): Disable

1 (ENABLE): Enable

IOCON

Enables clock for IOCON block.

0 (DISABLE): Disable

1 (ENABLE): Enable

GPIO0

Enables clock for GPIO0 port registers.

0 (DISABLE): Disable

1 (ENABLE): Enable

GPIO1

Enables clock for GPIO1 port registers.

0 (DISABLE): Disable

1 (ENABLE): Enable

GPIO2

Enables clock for GPIO2 port registers.

0 (DISABLE): Disable

1 (ENABLE): Enable

RESERVED

Reserved

PINT

Enables clock for pin interrupt block.

0 (DISABLE): Disable

1 (ENABLE): Enable

GINT

Enables clock for grouped pin interrupt block.

0 (DISABLE): Disable

1 (ENABLE): Enable

DMA

Enables clock for DMA.

0 (DISABLE): Disable

1 (ENABLE): Enable

CRC

Enables clock for CRC.

0 (DISABLE): Disable

1 (ENABLE): Enable

WWDT

Enables clock for WWDT.

0 (DISABLE): Disable

1 (ENABLE): Enable

RTC

Enables clock for RTC.

0 (DISABLE): Disable

1 (ENABLE): Enable

RESERVED

Reserved

ADC0

Enables clock for ADC0 register interface.

0 (DISABLE): Disable

1 (ENABLE): Enable

ADC1

Enables clock for ADC1 register interface.

0 (DISABLE): Disable

1 (ENABLE): Enable

DAC

Enables clock for DAC.

0 (DISABLE): Disable

1 (ENABLE): Enable

CMP

Enables clock to analog comparator block. This is the clock to the register interface for all 4 comparators.

0 (DISABLE): Disable

1 (ENABLE): Enable

RESERVED

Reserved

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